Vhdl programs - Free download as Word Doc (.doc), PDF File (.pdf), Text File (.txt) or read. A Parity generator creates the parity bit on the transmission side. Write VHDL code for 8 bit parity generator (with for loop and generic stat events).
I have completed a VHDL 16-bit parity generator and I would like to know if I have programmed it correctly. I have compiled it 10 times and worked out any bugs that it found. I was finally able to compile it successfully. My problem is that I am trying to run a timing simulation to make sure it will work correctly but I am not sure what I should be looking for. The basic operation is to XOR the A and B inputs to perform an iterative process with an output of '1' as odd and an output of '0' as even.
My code is written such that a basic XOR block is then added as a component of the complete parity generator. I would like a second opinion to make sure I have written it correctly and if it will do what it is designed to do.
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I thank you all in advance and look forward to any input, good or bad. Basic XOR gate block VHDL Code library ieee; use ieee.std_logic_1164.all; entity xor_gate is port( a: in std_logic; b: in std_logic; pari: in std_logic; paro: out std_logic); end xor_gate; architecture behavior of xor_gate is begin paro. As mentioned in the comments the or part of your 'xor_gate' prevents it from actually working as an xor gate to calculate bit parity. Instead your paro signal will be '0' when a=b and '1' when a/=b (the 16 bit vectors, not the bits within xor_gate).
If that was your intended functionality, then paro.
When valid_in is ‘1’ it will accept serial input and that serial input goes for parallel output. After receiving eight bit of serial input this block converts the serial input to parallel output. Valid_out signal goes ‘1’ after receiving eight bytes of serial data & gives parallel data on the data_o.
After valid_out goes high parity_out signal gives parity of the input data. Valid_out signal goes high on each eighth clock cycle & remain high for one cycle.